I went over all of Matt's tutorial to answer questions and correct mistakes, recorded a video to verify the outputs of the Adder lesson, finished creating the tutorial for Chapter 4 of Programming FPGAs, and created a tutorial on how to re-use a fresh constraint file in Vivado projects
I went through Matt's lessons and made some changes by the comments that I was confident changing. I also created a slideshow for a quick presentation on how to open and run old programs. If anyone has a suggestion for that slideshow or would like to make changes feel free to! After that I began going through Chapter 3 and will suggest feedback and changes to the PowerPoint tomorrow as I finish going through it, along with Chapter 4 and the re-using Constraint files PowerPoint.
For today I went through my video on Youtube and put timestamps in to make navigation easier. I reviewed the email that Professor White sent about some suggestions and will make some edits tomorrow. This is very much a side note but I have had my 3D printer just lying around and found a file of a case someone published for the Basys 3 board. I decided to print it and it came out pretty good. Maybe it would be good to have in case someone wanted to do the same for future labs, research, etc. The link is here: https://www.thingiverse.com/thing:3094814 .
I created a post for us to post the vocabularies that we see during our research and think they are worth to learn. I also went over the slides for the three lessons to add some trouble shooting slides some comments. I also spent sometimes looking through the book that Abril mentioned could be a resource for our project.
Yesterday I watched videos for understanding verilog. I found a playlist on youtube where there are different lessons for verilog. I posted this on the resources for fpga/verilog blog post. I also tested lesson 2 again to see if my outputs changed, but I am getting the same order as the first time.
Yesterday I went through and watched some more videos on FPGA and verilog, just to get used to using the board more and making myself more familiar with it. I also went through the lessons again, just to make sure I could still complete it on my own.
I went over all of Matt's tutorial to answer questions and correct mistakes, recorded a video to verify the outputs of the Adder lesson, finished creating the tutorial for Chapter 4 of Programming FPGAs, and created a tutorial on how to re-use a fresh constraint file in Vivado projects
ReplyDeleteIs the chapter 3 and 4 stuff posted somewhere, I would love to take a look.
DeleteI went through Matt's lessons and made some changes by the comments that I was confident changing. I also created a slideshow for a quick presentation on how to open and run old programs. If anyone has a suggestion for that slideshow or would like to make changes feel free to! After that I began going through Chapter 3 and will suggest feedback and changes to the PowerPoint tomorrow as I finish going through it, along with Chapter 4 and the re-using Constraint files PowerPoint.
ReplyDeleteFor today I went through my video on Youtube and put timestamps in to make navigation easier. I reviewed the email that Professor White sent about some suggestions and will make some edits tomorrow. This is very much a side note but I have had my 3D printer just lying around and found a file of a case someone published for the Basys 3 board. I decided to print it and it came out pretty good. Maybe it would be good to have in case someone wanted to do the same for future labs, research, etc. The link is here: https://www.thingiverse.com/thing:3094814 .
ReplyDeleteI created a post for us to post the vocabularies that we see during our research and think they are worth to learn. I also went over the slides for the three lessons to add some trouble shooting slides some comments. I also spent sometimes looking through the book that Abril mentioned could be a resource for our project.
ReplyDeleteYesterday I watched videos for understanding verilog. I found a playlist on youtube where there are different lessons for verilog. I posted this on the resources for fpga/verilog blog post. I also tested lesson 2 again to see if my outputs changed, but I am getting the same order as the first time.
ReplyDeleteYesterday I went through and watched some more videos on FPGA and verilog, just to get used to using the board more and making myself more familiar with it. I also went through the lessons again, just to make sure I could still complete it on my own.
ReplyDelete