Errors that have come up in Vivado

I wanted to make a post about some errors I've seen and personally run into in Vivado. I'll amend this post if/when more come up and please comment if you have had errors not listed here or any solutions

Errors can be found in the Messages at the bottom of the Vivado software and also come up when Synthesis, Implementation, and Bitstream generation fail.

"No constraints selected for write", this also comes along with a message "X out of X logical ports... etc.":

If you see this, this typically means that there is a problem with the constraints file. Make sure your input and output ports that are required are matched to the ports used in your block diagram or Verilog modules; they all must have exactly the same name! Also, check to make sure you are using Basys 3 board files and not those for another board. You can check the "Board" tab in the top left screen of Vivado (where sources, design, and signal are also tabs).  Be sure your board is correct before starting any project. If you have already started a project and want to change the board files, click Settings in Project Manager (on the left tab of the software), then click General under Project Settings. Select Project Device, search for Basys 3 and select it. Then hit Apply and exit out.